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High-level estimation and exploration of reliability for multi-processor system-on-chip

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Wang, Zheng Chattopadhyay, Anupam Springer Nature Singapore Pte Ltd. (Singapore, 2018) (eng) English 9789811010736 Computer architecture and design methodologies 1st ed. COMPUTER SOFTWARE--REUSABILITY; Unknown This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. .

Physical dimension
1 online resource (xx, 197 p.) Unknown ill. (in color.)

Summary / review / table of contents

Introduction --
Background --
Related Work --
High-level Fault Injection and Simulation --
Architectural Reliability Estimation --
Architectural Reliability Exploration --
System-level Reliability Exploration --
Conclusion and Outlook.


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Access no. Call number Location Status
01363/20 006.22 Wan H Online Available