Meinerzhagen, PascalTeman, Adam
Springer International Publishing (Cham, Switzerland , 2018) (eng) English9783319604022Unknown1st ed. SYSTEMS ON A CHIP; UnknownThis book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
Physical dimension
1 online resource (ix, 146 p.)Unknownill. (in color.)
Summary / review / table of contents
Motivation --
Introduction to Gain-Cell Based eDRAMs (GC-eDRAMs) --
GC-eDRAMs Operated at Scaled Supply Voltages --
Near-VT GC-eDRAM Implementations with Extended Retention Times --
Aggressive Technology and Voltage Scaling (to Sub-VT Domain) --
Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications --
4T Gain-Cell with Internal-Feedback for Ultra-Low Retention Power at Scaled CMOS Nodes --
Multilevel GC-eDRAM (MLGC-eDRAM) --
Soft Error Tolerant Low Power 4T Gain-Cell Array with Multi-Bit Error Detection and Correction --
Conclusions.